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The receive clock may have been recovered from the data by the serial clock recovery technique. The SIPO (Serial Input, Parallel Output) block typically has a receive clock output, a set of data output lines and output data latches. Implementations may also make use of a double-buffered register to avoid metastability when transferring data between clock domains. The simplest form of the PISO has a single shift register that receives the parallel data once per parallel clock, and shifts it out at the higher serial clock rate. It may use an internal or external phase-locked loop (PLL) to multiply the incoming parallel clock up to the serial frequency. The PISO (Parallel Input, Serial Output) block typically has a parallel clock input, a set of data input lines, and input data latches. There are 4 different SerDes architectures: (1) Parallel clock SerDes, (2) Embedded clock SerDes, (3) 8b/10b SerDes, (4) Bit interleaved SerDes. The basic SerDes function is made up of two functional blocks: the Parallel In Serial Out (PISO) block (aka Parallel-to-Serial converter) and the Serial In Parallel Out (SIPO) block (aka Serial-to-Parallel converter).